The present invention relates to silicon-on-insulator (SOI) structures, and more particularly to revealing active regions in SOI structures for devices under test (DUT) backside inspection.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for manufacturing, testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the possibility of manufacturing a defective device. It is also helpful to be able to perform the manufacture, testing and debugging of integrated circuits in an efficient and timely manner.
One type of circuit structure used in semiconductor devices is silicon-on insulator (SOI) structure. In typical SOI structures, an insulator layer is formed over a semiconductor die substrate, and a thin layer of silicon is formed on the insulator. Source and drain regions are then formed in the silicon layer and over the insulator. One advantage of such structure is that a transistor using the source and drain regions is able to switch faster than a transistor formed using conventional methods, due to reduced capacitance in the resulting structure. However, analysis of devices that employ SOI structure is challenging because accessing source, drain or other circuit regions often requires or at least benefits from destruction of a portion of the structure. The insulator portion of the SOI structure makes access to the active region difficult, particularly when inspection from the sample backside is desired, because the circuitry is formed under the insulator, as shown by the diagram of FIG. 1.
FIG. 1 illustrates a cross-sectional diagram of a typical SOI structure of a DUT with the arrangement of the layers demonstrating a backside approach to the active regions. As shown, the SOI structure includes a silicon substrate layer 10 having a buried oxide (BOX) layer 12 (e.g., silicon dioxide) disposed thereon. An active layer 14, also referred to as a silicon layer, is disposed on the BOX layer 12. As is commonly performed, the active regions of active layer 14 are silicided, i.e., a layer of refractory metal is provided that, when subjected to high enough temperature, reacts with silicon to form what is commonly called a xe2x80x9csilicidexe2x80x9d. Silicides are well known in the art and provide an area in which a dependable silicon contact with low ohmic resistance is formed. The silicided active regions include devices, such as transistors, which include a source 16, drain 18, and gate 20, which are separated by shallow trench isolation (STI) regions 22. Vias 24 (e.g., tungsten) connect the active regions devices to metal layers 26 (e.g., copper). When accessing the active regions of the SOI structure, the destruction of the silicon substrate layer 10 commonly occurs using a TMAH (tetramethylammonium hydroxide) etch. However, inspection of the active regions from the backside is inhibited, since the TMAH etch does not etch oxide and thus the BOX layer 12 remains.
Accordingly, a need exists for an approach to exposing active devices for DUT backside inspection of a SOI structure.
Aspects for revealing active regions of a silicon-on-insulator (SOI) circuit for inspection from a backside of a DUT are described. The aspects include etching a substrate layer of an SOI circuit and removing a buried oxide layer beneath the substrate layer. From these steps, active regions beneath the buried oxide layer are revealed.
With the present invention, a straightforward approach achieves a more direct view of the active regions as a result of the removal of the BOX layer in SOI structures. These and other advantages will become readily apparent from the following detailed description and accompanying drawings.